In an integrated circuit (an IC for infrared remote control reception, optical pickup signal reception, LED driving, etc.) provided in a vicinity of an electro-optic conversion element (such as a light-emitting diode) and an photo-electric conversion element (such as a photodiode), diffracted and scattered light due to signal light, and noise light such as fluorescent light generate a photocurrent at a parasitic photodiode, thereby causing circuit malfunction.
A p-type transistor, in particular, has a large area of an n-type epitaxial layer (base diffusion layer). Thus, the photocurrent at the parasitic photodiode increases a base current, thereby significantly affecting the circuit characteristics. This will be explained with reference to FIGS. 7 through 10.
FIG. 7 is a diagram schematically showing a structure of a p-type transistor 1, and FIG. 8 is its equivalent circuit diagram.
In this structure, an n-type epitaxial layer 3 is formed on a p-type substrate layer 2. The n-type epitaxial layer 3 is separated by a trench 4, and each separated n-type epitaxial layer 3 becomes an element region.
Here, because of the structure of the integrated circuit, a parasitic photodiode 5 is generated between the n-type epitaxial layer 3 and the substrate layer 2. Further, the parasitic photodiode 5 is connected between the base terminal of the p-type transistor 1 and the substrate layer 2 (ground).
Thus, as shown in FIG. 7, when light incidence causes a photocurrent Ipd that flows from the n-type epitaxial layer 3 toward the substrate 2, the photocurrent Ipd serves as a base current of the p-type transistor 1, thereby significantly affecting the circuit characteristics.
Because the photocurrent Ipd increases in accordance with an amount of incident light, the photocurrent Ipd increases when the p-type transistor 1 is located in a vicinity of the photo-electric conversion element. Further, since the photocurrent Ipd increases in accordance with an area S of the n-type epitaxial layer 3, the photocurrent Ipd increases in accordance with a current capacitance of the p-type transistor 1.
Likewise, FIG. 9 is a diagram schematically showing a structure of an n-type transistor 11, and FIG. 10 is its equivalent circuit diagram.
In this structure, an n-type epitaxial layer 13 is formed on a p-type substrate layer 12. The n-type epitaxial layer 13 is separated by a trench 14, and each separated n-type epitaxial layer 13 becomes an element region.
Here, because of the structure of the integrated circuit, a parasitic photodiode 15 is generated between the n-type epitaxial layer 13 and the substrate layer 12. Further, the parasitic photodiode 15 is connected between the collector terminal of the n-type transistor 11 and the substrate layer 12 (ground).
Thus, as shown in FIG. 9, when light incidence causes a photocurrent Ipd that flows from the n-type epitaxial layer 13 toward the substrate 12, the photocurrent Ipd bypasses a collector current of the n-type transistor 11, thereby significantly affecting the circuit characteristics.
The photocurrent Ipd increases in accordance with an amount of incident light, and increases in accordance with an area S of the n-type epitaxial layer 13. However, the n-type transistor 11 has larger current driving force compared with the p-type transistor 1, and can reduce the area S of the n-type epitaxial layer 13. Further, in the n-type transistor 11, the generated photocurrent influences the collector current, so that the influence of the photocurrent seems to be smaller by an amount corresponding to a current amplification ratio.
As a method to reduce the influences of the photocurrent due to the parasitic photodiodes 5 and 15, an element front face may be covered with wiring metal so as to shield light entering therefrom.
However, this method may not be able to sufficiently address light entering from a chip side face and a chip edge which cannot shield light. Further, in these years, because of the demand to cut costs by reducing a chip area and the number of masks, the wiring metal can no longer shield light sufficiently. Further, in accordance with the trend for low current consumption to save energy, the influence of the photocurrent due to the parasitic photodiode are relatively increasing.
Japanese Unexamined Patent Publication No. 262153/1991 (Tokukaihei 3-262153, published on Nov. 21, 1991; corresponding to Japanese Patent Publication No. 2634679) discloses a typical conventional technique that eliminates the influence of the photocurrent due to the parasitic photodiode in terms of circuit configuration.
FIG. 11 is an electric circuit diagram in which the conventional technique is applied to a current mirror circuit. This current mirror circuit 20 has a current mirror section 21 composed of a pair of p-type transistors q1 and q2.
The emitters of the transistors q1 and q2 are both connected to a high-level power supply. Further, the input-side transistor q1 has a diode structure in which the base and the collector are connected with each other. From the base and collector, a signal current iin is drawn out by a signal source 22.
The base of the output-side transistor q2 is connected to the base and collector of the transistor q1. Thus, the collector of the output-side transistor q2 outputs an output current iout, which is the signal current iin that is mirrored by a current ratio i2/i1 of the transistors q1 and q2.
When areas of the n-type epitaxial layers of the transistors q1 and q2 are s1 and s2, respectively, a photocurrent ipd flowing out from the bases of the transistors q1 and q2 is expressed as follows:ipd=(s1+s2)×io,  (1)where io is a value of photocurrent per unit area of the n-type epitaxial layer.
To compensate the photocurrent ipd, a current mirror section 23 composed of a pair of p-type transistors q3 and q4 is provided. The emitters of the transistors q3 and q4 are both connected to a high-level power supply. Further, the input-side transistor q3 has a diode structure in which the base and the connector are connected with each other. The base of the output-side transistor q4 is connected to the base and collector of the transistor q3.
Thus, the collector of the output-side transistor q4 outputs a compensation current ic, which is obtained by amplifying a photocurrent ipdc that flows out from the bases of the transistors q3 and q4. The compensation current ic is then supplied to the bases of the transistors q1 and q2.
When areas of the n-type epitaxial layers of the transistors q3 and q4 are s3 and s4, respectively, the photocurrent ipd is expressed as follows.ipdc=(s3+s4)×io  (2)
Then, for simplicity, the base currents of the transistors q3 and q4 are ignored, namely, a current amplification ratio hfe is assumed to ∞ (infinity). Here, when areas of the n-type epitaxial layers of the transistors q1, q2, q3, and q4 are s1, s2, s3, and s4, respectively, and i2/i1 and i4/i3 are current ratios of the current mirror sections 21 and 23, respectively, Kirchhoff law gives the following equations.ic=(i4/i3)×(s3+s4)×io  (3)iout=(i2/i1)×(iin+(s1+s2)×io−ic)  (4)
These two equations further derive the following equation.iout=(i2/i1)×(iin+((s1+s2)−(i4/i3)×(s3+s4))×io)  (5)
Therefore, by satisfying the following equation (6), a parasitic photodiode ic generated at a parasitic photodiode pdc of the transistors q3 and q4 can cancel the photocurrent ipd generated at a parasitic photodiode pd of the transistors q1 and q2.(s1+s2)=(i4/i3)×(s3+s4)  (6)
However, the current mirror circuit 20 has problems (a) and (b) as shown below.
(a) Because the output impedance of the output transistor q2 is low, variation in a collector-emitter voltage Vce (q2) of the output transistor q2 varies the output current iout. Namely, the dependence of the collector current Ic of a transistor on the collector-emitter voltage Vce is generally expressed as follows.Ic=Is×(1+Vce/Va)×exp(Vbe/Vt)  (7)where Is is a saturation current of the transistor, Va is Early voltage, Vbe is a base-emitter voltage, and Vt is kt/q (where k is the Boltzmann constant, T is the absolute temperature, and q is an elementary charge of electron).
Therefore, applying this to the equation (5) derives the following equation.iout=(Va+Vce (q2))/(Va +Vce (q1))×(i2/i1)×iin  (8)This shows that variation in the collector-emitter voltages Vce (q1) and Vce (q2) varies the output current iout.
(b) The strong influence of the base current causes an error in the output current. Namely, in the above-described calculation, the influence of the base current is ignored, namely, the current amplification ratio hfe is assumed to ∞, for simplicity. However, an actual value of the current amplification rate hfe is generally about 100, and thus influence thereof is not negligible.
A base current ib is expressed as follows.ib=ic/hfe  (9)
Further, base currents ib (q1) and ib (q2) of the transistors q1 and q2 directly affect the input current iin. Thus, the output current iout is expressed as follows.iout=(hfe/(hfe+1+i2/i1))×(i2/i1)×iin  (10)This shows that the base current ib causes an error in the output current iout. Further, the current amplification ratio hfe relates to the collector current ic. Namely, a minute collector current tends to decrease the current amplification ratio hfe. Thus, such a minute current increases the error in the base current ib.
To solve these problems, Japanese Unexamined Patent Publication No. 45536/1994 (Tokukaihei 6-45536, published on Feb. 18, 1994; corresponding to Japanese Patent Publication No. 2906387) discloses another conventional technique that eliminates the influence of the photocurrent due to the parasitic photodiode in terms of circuitry.
FIG. 12 is an electric circuit diagram in which the conventional technique is applied to a current mirror circuit.
Note that, this current mirror circuit 30 is similar to the current mirror circuit 20, and identical members with those used in the previous explanation are assigned, thus their explanation is omitted here.
As shown in FIG. 12, the current mirror sections 21 and 23 are arranged similarly to those in the previous arrangement. Notable in the current mirror circuit 30 is that the current mirror circuit 30 is provided with an output transistor q5.
The emitter of the output transistor q5 is supplied with a collector current of the output-side transistor q2 having a diode structure in which the base and the collector are connected with each other. The base of the output transistor q5 is connected to the collector of the input-side transistor q1. The collector of the output transistor q5 outputs an output current.
Further, with respect to the output transistor q5, a current mirror section 31 composed of a pair of p-type transistors q6 and q7 is also provided to compensate its photocurrent ipd5.
The emitters of the transistors q6 and q7 are both connected to a high-level power supply. The input-side transistor q6 has a diode structure in which the base and the collector are connected with each other. The base of the output-side transistor q7 is connected to the base of the transistor q5 and the collector of the transistor q1. The collector of the transistor q7 is connected to the base of the output transistor q5, namely the collector of the transistor q1.
By additionally providing the output transistor q5, the current mirror circuit 30 can keep the collector-emitter voltages Vce (q1) and Vce (q2) of the transistors q1 and q2 to be constant, even when a collector voltage Vce (q5) of the output transistor q5 varies. This can reduce the variation in the output current iout, thus addressing the problem (a).
Further, as for the problem (b), an amount of the base currents ib (q1) and ib (q2) of the transistors q1 and q2 that affects the input current iin can be reduced to 1/hfe by the output transistor q5.
As described above, the current mirror circuit 30 is a high-precision current mirror circuit that improves the output impedance and compensates the base currents ib (q1) and ib (q2).
The above-described conventional techniques eliminate the need for taking special measures to shield light, such as covering the element front face with wiring metal. However, the need to provide the current mirror sections 23 and 31 causes a problem of increasing a chip area and costs.